report_05-07-2025_04-17-07.html

Report generated on 07-May-2025 at 04:31:26 by pytest-html v3.2.0

Summary

920 tests ran in 858.89 seconds.

870 passed, 0 skipped, 50 failed, 0 errors, 0 expected failures, 0 unexpected passes

Results

Result Test TIDL Subgraphs Complete TIDL Offload Duration Links
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_707] 1 True 20.43
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_707'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_707', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=3889291 parent=3888034 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.379s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4011s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4021s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18856213 bytes MEM: Free's : 26 free's of 18856213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:17:40.347049947 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_727] 1 True 18.25
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_727'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_727', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=3889298 parent=3887711 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9745s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9776s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18786653 bytes MEM: Free's : 26 free's of 18786653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:17:38.027653696 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_712] 1 True 11.80
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_712'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_712', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3891367 parent=3887714 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8725s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8756s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18786637 bytes MEM: Free's : 26 free's of 18786637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:17:42.675027857 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_741] 1 True 14.37
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_741'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_741', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3893916 parent=3888034 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3578s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3588s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778949 bytes MEM: Free's : 26 free's of 18778949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:17:54.856824868 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_706] 1 True 600.55
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_706'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_706', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -15
E assert -15 == 0
E + where -15 = <Process name='Process-3' pid=3895975 parent=3887795 stopped exitcode=-SIGTERM>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= 0.39565s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.39670s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.39674s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.39679s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.39684s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.39705s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.39713s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_736] 1 True 6.56
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_736'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_736', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3901093 parent=3887714 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1258s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1261s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18779229 bytes MEM: Free's : 26 free's of 18779229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:18:14.295950744 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_702] 1 True 600.11
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_702'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_702', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: None
E assert None == 0
E + where None = <Process name='Process-8' pid=3901829 parent=3887718 started>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= 0.8143s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.8149s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.8150s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.8151s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.8152s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.8154s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.8156s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_710] 1 True 16.51
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_710'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_710', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3904448 parent=3888300 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7248s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18809745 bytes MEM: Free's : 26 free's of 18809745 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:18:32.846904460 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_725] 1 True 600.12
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_725'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_725', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: None
E assert None == 0
E + where None = <Process name='Process-6' pid=3905015 parent=3887757 started>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2940s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2949s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= 0.31591s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.31620s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.31623s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.31625s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.31629s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.31647s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.31660s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_724] 1 True 600.13
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_724'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_724', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: None
E assert None == 0
E + where None = <Process name='Process-7' pid=3911757 parent=3888198 started>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.374s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5799s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5815s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= 0.33303s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.33326s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.33329s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.33332s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.33335s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.33349s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.33355s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_729] 1 True 9.24
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_729'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_729', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3911763 parent=3887714 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7045s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18790661 bytes MEM: Free's : 26 free's of 18790661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
corrupted size vs. prev_size Aborted (core dumped) 2025-05-07 04:18:51.400506973 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_735] 1 True 12.55
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_735'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_735', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3911927 parent=3888290 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8366s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778997 bytes MEM: Free's : 26 free's of 18778997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:18:55.172384579 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_721] 1 True 600.11
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_721'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_721', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: None
E assert None == 0
E + where None = <Process name='Process-11' pid=3912475 parent=3887792 started>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7587s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= 0.49572s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.49634s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.49638s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.49640s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.49644s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.49669s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.49685s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_738] 1 True 14.04
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_738'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_738', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3914402 parent=3888560 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.241s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3027s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3037s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778997 bytes MEM: Free's : 26 free's of 18778997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:19:03.720165278 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_723] 1 True 15.58
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_723'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_723', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3915505 parent=3888290 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2730s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18780769 bytes MEM: Free's : 26 free's of 18780769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:19:11.036129971 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_734] 1 True 7.81
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_734'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_734', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3918221 parent=3888560 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18779461 bytes MEM: Free's : 26 free's of 18779461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:19:11.816665295 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_703] 1 True 10.39
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_703'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_703', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3925642 parent=3887962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.369s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18856213 bytes MEM: Free's : 26 free's of 18856213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:19:38.081135658 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_732] 1 True 13.05
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_732'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_732', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3927806 parent=3888396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.447s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7014s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18779461 bytes MEM: Free's : 26 free's of 18779461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:19:48.231566339 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_728] 1 True 9.50
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_728'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_728', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3928989 parent=3887962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.416s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7049s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7068s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18784649 bytes MEM: Free's : 26 free's of 18784649 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:19:47.878046459 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_742] 1 True 8.58
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_742'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_742', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3929595 parent=3887714 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.233s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2124s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2133s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778921 bytes MEM: Free's : 26 free's of 18778921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:19:48.669028768 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_717] 1 True 9.30
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_717'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_717', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3931782 parent=3888627 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.361s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7425s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18780765 bytes MEM: Free's : 26 free's of 18780765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:19:57.712074697 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_711] 1 True 12.37
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_711'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_711', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3933056 parent=3887996 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6549s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6566s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18784637 bytes MEM: Free's : 26 free's of 18784637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:20:04.791806944 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_737] 1 True 600.13
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_737'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_737', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: None
E assert None == 0
E + where None = <Process name='Process-22' pid=3935079 parent=3888189 started>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= 0.43506s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.43539s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.43542s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.43545s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.43550s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.43573s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.43584s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_726] 1 True 7.91
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_726'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_726', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3937367 parent=3888300 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6345s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18780769 bytes MEM: Free's : 26 free's of 18780769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:20:15.110637090 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_731] 1 True 7.42
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_731'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_731', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3937740 parent=3888627 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.199s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1942s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18779461 bytes MEM: Free's : 26 free's of 18779461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:20:16.840737025 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_740] 1 True 600.13
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_740'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_740', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: None
E assert None == 0
E + where None = <Process name='Process-19' pid=3938371 parent=3887702 started>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.233s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2229s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= 0.20713s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.20735s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.20739s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.20741s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.20746s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.20758s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.20765s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_747] 1 True 9.91
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_747'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_747', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3938686 parent=3887714 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.403s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6806s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6826s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778921 bytes MEM: Free's : 26 free's of 18778921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:20:22.528527127 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_716] 1 True 600.10
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_716'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_716', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: None
E assert None == 0
E + where None = <Process name='Process-19' pid=3940572 parent=3888524 started>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5608s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= 0.31698s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.31717s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.31721s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.31723s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.31727s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.31737s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.31742s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_714] 1 True 9.75
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_714'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_714', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3942677 parent=3887711 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4738s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4744s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18780765 bytes MEM: Free's : 26 free's of 18780765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:20:34.825704140 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_720] 1 True 9.07
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_720'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_720', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3943981 parent=3887996 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4988s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4996s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18790509 bytes MEM: Free's : 26 free's of 18790509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:20:38.289106579 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_705] 1 True 6.97
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_705'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_705', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3949182 parent=3888627 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.354s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5248s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5255s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18856213 bytes MEM: Free's : 26 free's of 18856213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:20:53.760629050 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_749] 1 True 6.98
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_749'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_749', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3949744 parent=3888396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4964s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4973s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18779133 bytes MEM: Free's : 26 free's of 18779133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:20:54.917899219 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_746] 1 True 7.62
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_746'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_746', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3955026 parent=3888396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6292s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6303s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778921 bytes MEM: Free's : 26 free's of 18778921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:21:11.611574690 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_708] 1 True 10.19
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_708'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_708', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3955488 parent=3887708 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.383s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6151s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6161s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19042085 bytes MEM: Free's : 26 free's of 19042085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:21:15.367418746 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_745] 1 True 9.17
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_745'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_745', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3956751 parent=3887714 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6261s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778921 bytes MEM: Free's : 26 free's of 18778921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:21:19.353569624 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_704] 1 True 7.55
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_704'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_704', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3958280 parent=3887705 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5380s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18856213 bytes MEM: Free's : 26 free's of 18856213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:21:23.092332248 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_713] 1 True 8.57
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_713'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_713', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3958309 parent=3887708 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5030s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18782765 bytes MEM: Free's : 26 free's of 18782765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:21:24.130002340 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_744] 1 True 7.91
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_744'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_744', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3958910 parent=3887711 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4621s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4628s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18779189 bytes MEM: Free's : 26 free's of 18779189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:21:25.248433370 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_709] 1 True 600.13
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_709'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_709', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: None
E assert None == 0
E + where None = <Process name='Process-29' pid=3960408 parent=3887722 started>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4438s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= 0.28559s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.28571s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.28574s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.28576s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.28580s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.28593s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.28598s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_750] 1 True 8.26
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_750'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_750', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3960982 parent=3887996 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.190s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1594s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778921 bytes MEM: Free's : 26 free's of 18778921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:21:32.883354419 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_748] 1 True 6.92
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_748'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_748', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3975102 parent=3888627 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.197s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3265s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3269s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778921 bytes MEM: Free's : 26 free's of 18778921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:22:16.250691000 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_743] 1 True 6.20
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_743'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_743', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3976942 parent=3887711 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5058s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5066s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778921 bytes MEM: Free's : 26 free's of 18778921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:22:21.457217967 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_701] 1 True 5.77
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_701'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_701', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3980660 parent=3888034 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4721s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4728s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18809745 bytes MEM: Free's : 26 free's of 18809745 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:22:31.602741505 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_739] 1 True 7.16
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_739'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_739', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3992626 parent=3888300 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.869s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6849s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6861s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778997 bytes MEM: Free's : 26 free's of 18778997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:23:21.314771284 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_733] 1 True 6.67
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_733'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_733', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3992974 parent=3888396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18779461 bytes MEM: Free's : 26 free's of 18779461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:23:21.618888048 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_719] 1 True 9.35
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_719'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_719', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3993277 parent=3888031 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.229s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3787s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3792s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18784637 bytes MEM: Free's : 26 free's of 18784637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:23:24.756627218 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_715] 1 True 8.50
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_715'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_715', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3993496 parent=3887714 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18780765 bytes MEM: Free's : 26 free's of 18780765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:23:24.371432001 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_722] 1 True 5.21
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_722'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_722', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3994239 parent=3887862 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.141s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1933s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1936s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18784649 bytes MEM: Free's : 26 free's of 18784649 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:23:26.536493798 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_718] 1 True 4.87
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_718'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_718', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3997284 parent=3888396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.192s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3079s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18780765 bytes MEM: Free's : 26 free's of 18780765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:23:35.432932056 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_730] 1 True 2.46
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_730'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'ScatterND_730', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3998993 parent=3888290 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1308s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 34304 -- [tidl_import_core.cpp, 690] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1793] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 4072] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4408] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5314] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4606] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1516] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1961] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18784649 bytes MEM: Free's : 26 free's of 18784649 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
double free or corruption (!prev) Aborted (core dumped) 2025-05-07 04:23:38.449405480 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed.
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_611] 0 - 0.36
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_508] 1 True 24.71
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6488s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6503s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38840525 bytes MEM: Free's : 26 free's of 38840525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_402] 1 True 11.17
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4267s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4283s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 78596401 bytes MEM: Free's : 26 free's of 78596401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_537] 1 True 11.55
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4258s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73243301 bytes MEM: Free's : 26 free's of 73243301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_556] 0 - 0.35
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_119] 1 True 16.17
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.373s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4232s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4244s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733201 bytes MEM: Free's : 26 free's of 18733201 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_755] 0 - 0.34
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_366] 1 True 21.45
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2888s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2896s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 61452005 bytes MEM: Free's : 26 free's of 61452005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_427] 1 True 18.87
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3234s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3253s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76209481 bytes MEM: Free's : 26 free's of 76209481 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_833] 0 - 0.16
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_77] 1 True 16.69
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.77s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.80s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.589s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9503s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729541 bytes MEM: Free's : 26 free's of 18729541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_302] 1 True 22.14
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5634s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27242389 bytes MEM: Free's : 26 free's of 27242389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_539] 1 True 22.12
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73243301 bytes MEM: Free's : 26 free's of 73243301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_242] 1 True 17.76
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8682s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21154517 bytes MEM: Free's : 26 free's of 21154517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_246] 1 True 21.63
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.562s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9389s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9417s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21666557 bytes MEM: Free's : 26 free's of 21666557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_623] 0 - 0.51
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_663] 0 - 0.43
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_95] 1 True 17.13
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7363s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18754037 bytes MEM: Free's : 26 free's of 18754037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_359] 1 True 11.73
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74034897 bytes MEM: Free's : 26 free's of 74034897 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_523] 1 True 17.51
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5703s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 75333293 bytes MEM: Free's : 26 free's of 75333293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_390] 1 True 11.13
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4592s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58306405 bytes MEM: Free's : 26 free's of 58306405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_55] 1 True 11.14
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4063s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730549 bytes MEM: Free's : 26 free's of 18730549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_280] 1 True 17.62
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4211s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4224s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29339345 bytes MEM: Free's : 26 free's of 29339345 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_612] 0 - 0.48
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_399] 1 True 12.56
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4182s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4197s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 107240261 bytes MEM: Free's : 26 free's of 107240261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_201] 1 True 23.49
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7905s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7923s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19771093 bytes MEM: Free's : 26 free's of 19771093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_138] 1 True 10.25
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4113s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4129s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18765525 bytes MEM: Free's : 26 free's of 18765525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_66] 1 True 19.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.408s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6608s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6629s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18735901 bytes MEM: Free's : 26 free's of 18735901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_251] 1 True 10.13
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4086s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21055985 bytes MEM: Free's : 26 free's of 21055985 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_856] 0 - 0.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_368] 1 True 13.97
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4635s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4649s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59354837 bytes MEM: Free's : 26 free's of 59354837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_440] 1 True 17.97
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4029s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4041s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70904305 bytes MEM: Free's : 26 free's of 70904305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_454] 1 True 23.09
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.602s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7857s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7883s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46745941 bytes MEM: Free's : 26 free's of 46745941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_166] 1 True 16.61
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4313s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18829021 bytes MEM: Free's : 26 free's of 18829021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_109] 1 True 15.08
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3294s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18734749 bytes MEM: Free's : 26 free's of 18734749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_828] 0 - 0.40
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_268] 1 True 12.76
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11220s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11252s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21052285 bytes MEM: Free's : 26 free's of 21052285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_664] 0 - 0.53
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_162] 1 True 21.85
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7953s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7979s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18829021 bytes MEM: Free's : 26 free's of 18829021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_235] 1 True 11.45
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6649s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22280921 bytes MEM: Free's : 26 free's of 22280921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_398] 1 True 15.06
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5792s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5815s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 107240261 bytes MEM: Free's : 26 free's of 107240261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_669] 0 - 0.37
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_285] 1 True 13.92
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.256s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28028645 bytes MEM: Free's : 26 free's of 28028645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_778] 0 - 0.36
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_414] 1 True 12.88
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76216457 bytes MEM: Free's : 26 free's of 76216457 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_346] 1 True 15.54
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31113109 bytes MEM: Free's : 26 free's of 31113109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_515] 1 True 15.79
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7884s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 80924377 bytes MEM: Free's : 26 free's of 80924377 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_596] 0 - 0.43
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_804] 0 - 0.28
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_324] 1 True 13.39
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5088s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31522517 bytes MEM: Free's : 26 free's of 31522517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_335] 1 True 20.11
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8882s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8902s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31118053 bytes MEM: Free's : 26 free's of 31118053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_245] 1 True 15.35
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7658s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7681s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21666557 bytes MEM: Free's : 26 free's of 21666557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_252] 1 True 16.67
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.41s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.541s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21057277 bytes MEM: Free's : 26 free's of 21057277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_610] 0 - 0.44
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_681] 0 - 0.35
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_6] 1 True 15.15
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2548s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18732657 bytes MEM: Free's : 26 free's of 18732657 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_354] 1 True 12.71
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3639s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3654s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 121220825 bytes MEM: Free's : 26 free's of 121220825 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_76] 1 True 18.84
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6986s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7007s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729485 bytes MEM: Free's : 26 free's of 18729485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_822] 0 - 0.41
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_142] 1 True 24.08
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5822s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5845s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764641 bytes MEM: Free's : 26 free's of 18764641 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_679] 0 - 0.39
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_831] 0 - 0.34
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_800] 0 - 0.35
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_862] 0 - 0.50
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_566] 0 - 0.36
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_423] 1 True 15.73
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3894s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76209681 bytes MEM: Free's : 26 free's of 76209681 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_362] 1 True 24.12
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8515s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59354837 bytes MEM: Free's : 26 free's of 59354837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_446] 1 True 25.74
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3119s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3136s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47499285 bytes MEM: Free's : 26 free's of 47499285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_544] 1 True 14.38
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8225s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73236629 bytes MEM: Free's : 26 free's of 73236629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_12] 1 True 10.74
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4312s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731321 bytes MEM: Free's : 26 free's of 18731321 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_754] 0 - 0.44
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_279] 1 True 14.30
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3999s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4013s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31436501 bytes MEM: Free's : 26 free's of 31436501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_642] 0 - 0.44
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_257] 1 True 21.38
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3066s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3078s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21053401 bytes MEM: Free's : 26 free's of 21053401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_609] 0 - 0.37
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_577] 0 - 0.36
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_182] 1 True 25.14
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6039s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796637 bytes MEM: Free's : 26 free's of 18796637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_769] 0 - 0.41
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_191] 1 True 25.21
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5878s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20098777 bytes MEM: Free's : 26 free's of 20098777 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_79] 1 True 22.36
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.369s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3331s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729541 bytes MEM: Free's : 26 free's of 18729541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_15] 1 True 23.96
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.225s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2230s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2239s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18732665 bytes MEM: Free's : 26 free's of 18732665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_283] 1 True 21.53
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27504341 bytes MEM: Free's : 26 free's of 27504341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_492] 1 True 22.64
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5308s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38843137 bytes MEM: Free's : 26 free's of 38843137 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_90] 1 True 13.71
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.376s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5173s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5213s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729677 bytes MEM: Free's : 26 free's of 18729677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_788] 0 - 0.35
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_693] 0 - 0.40
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_82] 1 True 20.67
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8045s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729509 bytes MEM: Free's : 26 free's of 18729509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_453] 1 True 21.92
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.245s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3230s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3233s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46735401 bytes MEM: Free's : 26 free's of 46735401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_338] 1 True 12.33
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.696s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5145s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5170s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31118053 bytes MEM: Free's : 26 free's of 31118053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_36] 1 True 17.06
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8318s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8343s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731153 bytes MEM: Free's : 26 free's of 18731153 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_9] 1 True 19.45
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4375s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4380s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731317 bytes MEM: Free's : 26 free's of 18731317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_413] 1 True 19.09
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.373s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6016s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6030s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76216457 bytes MEM: Free's : 26 free's of 76216457 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_810] 0 - 0.40
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_756] 0 - 0.36
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_490] 1 True 18.09
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3158s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39308269 bytes MEM: Free's : 26 free's of 39308269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_96] 1 True 17.88
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4478s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4483s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18748305 bytes MEM: Free's : 26 free's of 18748305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_207] 1 True 17.56
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1193s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19771093 bytes MEM: Free's : 26 free's of 19771093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_876] 0 - 0.43
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_157] 1 True 15.99
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4045s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4051s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18812625 bytes MEM: Free's : 26 free's of 18812625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_355] 1 True 15.76
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.170s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2478s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2483s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74034897 bytes MEM: Free's : 26 free's of 74034897 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_234] 1 True 15.21
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.141s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1455s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1460s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21461713 bytes MEM: Free's : 26 free's of 21461713 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_901] 0 - 0.18
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_536] 1 True 9.54
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.206s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3049s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3051s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73246649 bytes MEM: Free's : 26 free's of 73246649 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_915] 0 - 0.23
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_581] 0 - 0.27
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_381] 1 True 8.55
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.169s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2637s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2639s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58306405 bytes MEM: Free's : 26 free's of 58306405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_662] 0 - 0.18
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_220] 1 True 6.54
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.131s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1850s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1851s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19706585 bytes MEM: Free's : 26 free's of 19706585 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_622] 0 - 0.10
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_342] 1 True 6.28
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31113061 bytes MEM: Free's : 26 free's of 31113061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_700] 0 - 0.09
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_767] 0 - 0.08
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_907] 0 - 0.10
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_200] 1 True 4.52
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20229853 bytes MEM: Free's : 26 free's of 20229853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_502] 1 True 5.39
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3796s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3803s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38840501 bytes MEM: Free's : 26 free's of 38840501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_496] 1 True 5.14
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.219s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4164s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4170s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38865313 bytes MEM: Free's : 26 free's of 38865313 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_451] 1 True 12.01
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.585s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11692s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11726s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46735401 bytes MEM: Free's : 26 free's of 46735401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_97] 1 True 9.74
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.573s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18742573 bytes MEM: Free's : 26 free's of 18742573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_460] 1 True 15.48
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.239s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3007s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3012s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46753181 bytes MEM: Free's : 26 free's of 46753181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_273] 1 True 12.43
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9166s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9179s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29339345 bytes MEM: Free's : 26 free's of 29339345 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_275] 1 True 14.03
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.251s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29339345 bytes MEM: Free's : 26 free's of 29339345 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_485] 1 True 11.20
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3135s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39776189 bytes MEM: Free's : 26 free's of 39776189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_586] 0 - 0.18
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_217] 1 True 10.61
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4164s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19706585 bytes MEM: Free's : 26 free's of 19706585 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_438] 1 True 17.55
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6452s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 60544733 bytes MEM: Free's : 26 free's of 60544733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_410] 1 True 16.18
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9373s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 77005073 bytes MEM: Free's : 26 free's of 77005073 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_263] 1 True 14.04
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3087s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3101s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21052309 bytes MEM: Free's : 26 free's of 21052309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_57] 1 True 10.68
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730529 bytes MEM: Free's : 26 free's of 18730529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_692] 0 - 0.26
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_71] 1 True 16.77
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4730s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4741s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730445 bytes MEM: Free's : 26 free's of 18730445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_889] 0 - 0.31
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_155] 1 True 19.96
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8111s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8130s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18853593 bytes MEM: Free's : 26 free's of 18853593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_806] 0 - 0.33
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_776] 0 - 0.27
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_88] 1 True 20.25
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8042s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8065s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729449 bytes MEM: Free's : 26 free's of 18729449 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_639] 0 - 0.37
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_433] 1 True 11.25
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70904305 bytes MEM: Free's : 26 free's of 70904305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_884] 0 - 0.30
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_137] 1 True 11.90
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4989s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18765525 bytes MEM: Free's : 26 free's of 18765525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_608] 0 - 0.42
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_411] 1 True 13.02
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.394s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6571s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6591s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76223633 bytes MEM: Free's : 26 free's of 76223633 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_172] 1 True 17.71
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6621s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18797809 bytes MEM: Free's : 26 free's of 18797809 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_682] 0 - 0.45
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_167] 1 True 20.65
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7850s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7867s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18812629 bytes MEM: Free's : 26 free's of 18812629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_516] 1 True 21.83
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7662s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7697s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 127051605 bytes MEM: Free's : 26 free's of 127051605 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_293] 1 True 16.73
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.416s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6325s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27244249 bytes MEM: Free's : 26 free's of 27244249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_317] 1 True 13.25
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7289s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58146525 bytes MEM: Free's : 26 free's of 58146525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_388] 1 True 11.39
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7282s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58306405 bytes MEM: Free's : 26 free's of 58306405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_428] 1 True 14.31
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.243s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2473s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76209433 bytes MEM: Free's : 26 free's of 76209433 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_98] 1 True 18.89
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18736841 bytes MEM: Free's : 26 free's of 18736841 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_624] 0 - 0.36
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_576] 0 - 0.35
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_112] 1 True 11.70
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.231s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2408s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2415s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733161 bytes MEM: Free's : 26 free's of 18733161 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_249] 1 True 11.61
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5905s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5925s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21154517 bytes MEM: Free's : 26 free's of 21154517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_37] 1 True 14.56
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4766s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4774s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731925 bytes MEM: Free's : 26 free's of 18731925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_210] 1 True 15.02
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.406s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20098813 bytes MEM: Free's : 26 free's of 20098813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_13] 1 True 13.79
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.200s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2327s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18732665 bytes MEM: Free's : 26 free's of 18732665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_772] 0 - 0.34
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_547] 1 True 13.14
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5458s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73236877 bytes MEM: Free's : 26 free's of 73236877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_226] 1 True 17.79
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.263s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4469s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19705701 bytes MEM: Free's : 26 free's of 19705701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_877] 0 - 0.35
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_101] 1 True 15.51
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5820s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5831s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733677 bytes MEM: Free's : 26 free's of 18733677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_218] 1 True 11.73
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.226s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2163s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2171s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19709693 bytes MEM: Free's : 26 free's of 19709693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_464] 1 True 15.04
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6559s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6570s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46731997 bytes MEM: Free's : 26 free's of 46731997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_386] 1 True 14.48
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7328s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58306405 bytes MEM: Free's : 26 free's of 58306405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_658] 0 - 0.37
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_486] 1 True 13.23
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8628s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8639s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40243981 bytes MEM: Free's : 26 free's of 40243981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_546] 1 True 11.26
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.373s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5690s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5702s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73236653 bytes MEM: Free's : 26 free's of 73236653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_920] 0 - 0.29
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_367] 1 True 11.81
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7579s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59354837 bytes MEM: Free's : 26 free's of 59354837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_841] 0 - 0.29
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_843] 0 - 0.27
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_498] 1 True 11.39
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.408s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5677s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5689s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38843137 bytes MEM: Free's : 26 free's of 38843137 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_851] 0 - 0.29
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_799] 0 - 0.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_448] 1 True 10.21
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.258s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47499285 bytes MEM: Free's : 26 free's of 47499285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_444] 1 True 10.92
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6163s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6176s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47499285 bytes MEM: Free's : 26 free's of 47499285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_659] 0 - 0.34
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_512] 1 True 11.34
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.249s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3014s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 88612277 bytes MEM: Free's : 26 free's of 88612277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_775] 0 - 0.25
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_864] 0 - 0.24
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_582] 0 - 0.25
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_676] 0 - 0.28
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_827] 0 - 0.26
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_183] 1 True 9.42
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5428s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796413 bytes MEM: Free's : 26 free's of 18796413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_673] 0 - 0.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_20] 1 True 11.82
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18734833 bytes MEM: Free's : 26 free's of 18734833 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_100] 1 True 14.84
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2742s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2752s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18754037 bytes MEM: Free's : 26 free's of 18754037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_92] 1 True 17.11
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6069s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6086s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18736841 bytes MEM: Free's : 26 free's of 18736841 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_126] 1 True 10.05
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18776793 bytes MEM: Free's : 26 free's of 18776793 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_255] 1 True 12.41
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7488s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7509s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21055985 bytes MEM: Free's : 26 free's of 21055985 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_506] 1 True 9.81
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7853s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7870s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38840749 bytes MEM: Free's : 26 free's of 38840749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_250] 1 True 9.16
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.424s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6375s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6389s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21154517 bytes MEM: Free's : 26 free's of 21154517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_677] 0 - 0.27
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_455] 1 True 13.23
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3109s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3117s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46735401 bytes MEM: Free's : 26 free's of 46735401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_888] 0 - 0.29
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_221] 1 True 17.64
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.451s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7507s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7518s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19705701 bytes MEM: Free's : 26 free's of 19705701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_296] 1 True 10.25
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27244249 bytes MEM: Free's : 26 free's of 27244249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_757] 0 - 0.27
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_760] 0 - 0.28
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_468] 1 True 14.49
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.426s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7162s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7178s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46732445 bytes MEM: Free's : 26 free's of 46732445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_357] 1 True 11.97
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.380s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5442s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5451s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 97627861 bytes MEM: Free's : 26 free's of 97627861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_550] 1 True 11.74
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.225s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2050s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2056s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73236677 bytes MEM: Free's : 26 free's of 73236677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_190] 1 True 11.19
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.202s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6623s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796837 bytes MEM: Free's : 26 free's of 18796837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_631] 0 - 0.34
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_204] 1 True 8.77
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.569s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2855s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2863s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19836637 bytes MEM: Free's : 26 free's of 19836637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_139] 1 True 13.93
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6908s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6921s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18765525 bytes MEM: Free's : 26 free's of 18765525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_387] 1 True 13.68
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.226s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2354s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58306429 bytes MEM: Free's : 26 free's of 58306429 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_848] 0 - 0.28
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_698] 0 - 0.34
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_205] 1 True 11.08
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.599s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7758s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7785s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19836637 bytes MEM: Free's : 26 free's of 19836637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_461] 1 True 10.85
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6904s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6919s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46731997 bytes MEM: Free's : 26 free's of 46731997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_533] 1 True 13.11
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.393s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6978s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73256821 bytes MEM: Free's : 26 free's of 73256821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_187] 1 True 12.22
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.389s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7254s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7267s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796837 bytes MEM: Free's : 26 free's of 18796837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_158] 1 True 11.10
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18812625 bytes MEM: Free's : 26 free's of 18812625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_436] 1 True 10.96
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.420s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6523s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53638353 bytes MEM: Free's : 26 free's of 53638353 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_52] 1 True 14.12
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.235s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5473s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730569 bytes MEM: Free's : 26 free's of 18730569 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_761] 0 - 0.25
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_33] 1 True 11.74
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6194s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18735781 bytes MEM: Free's : 26 free's of 18735781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_134] 1 True 9.86
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7336s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18765525 bytes MEM: Free's : 26 free's of 18765525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_802] 0 - 0.27
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_450] 1 True 13.93
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.226s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2273s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 51336229 bytes MEM: Free's : 26 free's of 51336229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_846] 0 - 0.26
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_351] 1 True 12.83
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5896s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5908s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 121220825 bytes MEM: Free's : 26 free's of 121220825 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_813] 0 - 0.20
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_364] 1 True 17.17
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5010s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5025s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 64597757 bytes MEM: Free's : 26 free's of 64597757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_881] 0 - 0.30
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_449] 1 True 12.08
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.226s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2214s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47499285 bytes MEM: Free's : 26 free's of 47499285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_240] 1 True 16.85
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5762s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5780s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21461713 bytes MEM: Free's : 26 free's of 21461713 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_654] 0 - 0.31
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_774] 0 - 0.26
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_259] 1 True 17.15
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6889s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6900s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21053401 bytes MEM: Free's : 26 free's of 21053401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_421] 1 True 11.69
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8107s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8126s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76209433 bytes MEM: Free's : 26 free's of 76209433 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_228] 1 True 11.23
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6873s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6888s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19705701 bytes MEM: Free's : 26 free's of 19705701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_458] 1 True 14.59
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5543s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5551s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46738957 bytes MEM: Free's : 26 free's of 46738957 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_41] 1 True 11.09
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.551s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730621 bytes MEM: Free's : 26 free's of 18730621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_593] 0 - 0.27
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_465] 1 True 12.06
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.429s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6983s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6998s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46731997 bytes MEM: Free's : 26 free's of 46731997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_793] 0 - 0.23
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_674] 0 - 0.27
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_836] 0 - 0.26
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_543] 1 True 11.40
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.234s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11869s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11885s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73236629 bytes MEM: Free's : 26 free's of 73236629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_791] 0 - 0.22
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_687] 0 - 0.29
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_145] 1 True 10.34
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5511s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5526s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764681 bytes MEM: Free's : 26 free's of 18764681 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_209] 1 True 11.64
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4022s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4029s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19771093 bytes MEM: Free's : 26 free's of 19771093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_585] 0 - 0.26
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_873] 0 - 0.26
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_892] 0 - 0.24
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_626] 0 - 0.24
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_527] 1 True 11.19
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.408s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5605s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 77429981 bytes MEM: Free's : 26 free's of 77429981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_563] 0 - 0.25
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_918] 0 - 0.26
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_181] 1 True 10.24
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.234s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1939s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1948s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796413 bytes MEM: Free's : 26 free's of 18796413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_442] 1 True 12.62
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.367s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5971s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5981s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 51336229 bytes MEM: Free's : 26 free's of 51336229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_314] 1 True 11.49
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.369s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5173s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5182s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36028113 bytes MEM: Free's : 26 free's of 36028113 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_118] 1 True 11.76
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3410s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733161 bytes MEM: Free's : 26 free's of 18733161 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_540] 1 True 13.46
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7743s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7765s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73239953 bytes MEM: Free's : 26 free's of 73239953 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_325] 1 True 14.42
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7456s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32341733 bytes MEM: Free's : 26 free's of 32341733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_169] 1 True 9.59
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2249s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18927357 bytes MEM: Free's : 26 free's of 18927357 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_657] 0 - 0.36
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_653] 0 - 0.34
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_298] 1 True 9.70
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27246309 bytes MEM: Free's : 26 free's of 27246309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_668] 0 - 0.31
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_814] 0 - 0.24
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_188] 1 True 13.46
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8179s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8194s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796389 bytes MEM: Free's : 26 free's of 18796389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_214] 1 True 8.55
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.389s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6339s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6357s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19707621 bytes MEM: Free's : 26 free's of 19707621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_646] 0 - 0.21
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_627] 0 - 0.19
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_899] 0 - 0.19
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_347] 1 True 9.00
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4551s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4559s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31113061 bytes MEM: Free's : 26 free's of 31113061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_786] 0 - 0.23
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_538] 1 True 13.98
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.403s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6878s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6912s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73249997 bytes MEM: Free's : 26 free's of 73249997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_70] 1 True 14.83
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.394s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7220s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731069 bytes MEM: Free's : 26 free's of 18731069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_466] 1 True 13.26
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.403s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5757s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5774s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46731997 bytes MEM: Free's : 26 free's of 46731997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_14] 1 True 10.57
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.232s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2067s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18732665 bytes MEM: Free's : 26 free's of 18732665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_176] 1 True 11.29
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3333s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796761 bytes MEM: Free's : 26 free's of 18796761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_513] 1 True 14.74
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5195s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 80924377 bytes MEM: Free's : 26 free's of 80924377 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_330] 1 True 9.81
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6636s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6650s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31522517 bytes MEM: Free's : 26 free's of 31522517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_753] 0 - 0.29
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_917] 0 - 0.35
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_815] 0 - 0.28
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_418] 1 True 11.67
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2569s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76216457 bytes MEM: Free's : 26 free's of 76216457 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_645] 0 - 0.29
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_694] 0 - 0.32
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_392] 1 True 17.35
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6366s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96896601 bytes MEM: Free's : 26 free's of 96896601 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_309] 1 True 14.76
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4396s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27242389 bytes MEM: Free's : 26 free's of 27242389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_93] 1 True 10.32
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18736841 bytes MEM: Free's : 26 free's of 18736841 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_81] 1 True 11.62
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.255s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3572s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729489 bytes MEM: Free's : 26 free's of 18729489 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_908] 0 - 0.32
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_382] 1 True 12.83
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6863s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6879s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58306429 bytes MEM: Free's : 26 free's of 58306429 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_871] 0 - 0.34
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_159] 1 True 12.08
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5223s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18812625 bytes MEM: Free's : 26 free's of 18812625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_291] 1 True 10.16
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5959s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5973s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27244249 bytes MEM: Free's : 26 free's of 27244249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_557] 0 - 0.29
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_313] 1 True 11.92
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.405s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5747s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 43400917 bytes MEM: Free's : 26 free's of 43400917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_409] 1 True 10.06
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5286s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 77005073 bytes MEM: Free's : 26 free's of 77005073 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_766] 0 - 0.22
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_500] 1 True 11.29
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6320s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38843137 bytes MEM: Free's : 26 free's of 38843137 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_680] 0 - 0.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_49] 1 True 11.32
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8098s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8120s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730565 bytes MEM: Free's : 26 free's of 18730565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_634] 0 - 0.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_17] 1 True 12.93
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.376s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6064s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6076s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731321 bytes MEM: Free's : 26 free's of 18731321 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_549] 1 True 11.21
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6665s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6679s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73236629 bytes MEM: Free's : 26 free's of 73236629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_867] 0 - 0.24
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_274] 1 True 10.10
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6758s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6776s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37727965 bytes MEM: Free's : 26 free's of 37727965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_792] 0 - 0.29
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_244] 1 True 16.77
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13959s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13972s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21256925 bytes MEM: Free's : 26 free's of 21256925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_294] 1 True 10.08
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.404s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5908s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27244249 bytes MEM: Free's : 26 free's of 27244249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_855] 0 - 0.23
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_395] 1 True 10.95
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.424s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7086s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7100s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 86552941 bytes MEM: Free's : 26 free's of 86552941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_807] 0 - 0.28
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_521] 1 True 12.12
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.377s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7031s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7048s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74634397 bytes MEM: Free's : 26 free's of 74634397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_597] 0 - 0.21
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_316] 1 True 10.45
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.409s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6677s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6688s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36028113 bytes MEM: Free's : 26 free's of 36028113 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_583] 0 - 0.28
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_878] 0 - 0.25
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_80] 1 True 15.42
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.245s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3438s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729485 bytes MEM: Free's : 26 free's of 18729485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_573] 0 - 0.28
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_64] 1 True 12.98
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.208s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2120s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730249 bytes MEM: Free's : 26 free's of 18730249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_604] 0 - 0.26
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_153] 1 True 12.60
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6642s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6660s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18853593 bytes MEM: Free's : 26 free's of 18853593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_128] 1 True 10.17
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5692s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5702s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18780893 bytes MEM: Free's : 26 free's of 18780893 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_59] 1 True 11.12
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6016s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6027s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730569 bytes MEM: Free's : 26 free's of 18730569 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_483] 1 True 12.63
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.387s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7527s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40243981 bytes MEM: Free's : 26 free's of 40243981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_333] 1 True 12.32
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5865s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5874s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31115481 bytes MEM: Free's : 26 free's of 31115481 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_78] 1 True 16.12
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6840s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6854s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729485 bytes MEM: Free's : 26 free's of 18729485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_35] 1 True 10.43
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.371s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5538s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5550s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731153 bytes MEM: Free's : 26 free's of 18731153 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_686] 0 - 0.35
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_121] 1 True 13.61
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.378s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6273s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793189 bytes MEM: Free's : 26 free's of 18793189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_215] 1 True 13.34
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7166s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7184s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19708657 bytes MEM: Free's : 26 free's of 19708657 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_105] 1 True 14.63
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18734213 bytes MEM: Free's : 26 free's of 18734213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_578] 0 - 0.26
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_900] 0 - 0.28
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_406] 1 True 12.40
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6804s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6819s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 83370513 bytes MEM: Free's : 26 free's of 83370513 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_115] 1 True 10.31
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7842s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7856s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733161 bytes MEM: Free's : 26 free's of 18733161 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_292] 1 True 13.32
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6532s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6544s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27248369 bytes MEM: Free's : 26 free's of 27248369 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_437] 1 True 13.11
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.329s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5023s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5032s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70904305 bytes MEM: Free's : 26 free's of 70904305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_311] 1 True 11.16
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7180s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36028113 bytes MEM: Free's : 26 free's of 36028113 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_858] 0 - 0.27
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_584] 0 - 0.27
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_638] 0 - 0.29
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_154] 1 True 11.09
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.194s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1901s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1910s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18812625 bytes MEM: Free's : 26 free's of 18812625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_344] 1 True 10.41
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.382s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31113061 bytes MEM: Free's : 26 free's of 31113061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_567] 0 - 0.27
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_223] 1 True 11.40
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10454s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19705701 bytes MEM: Free's : 26 free's of 19705701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_842] 0 - 0.23
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_62] 1 True 11.32
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.240s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730249 bytes MEM: Free's : 26 free's of 18730249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_829] 0 - 0.34
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_636] 0 - 0.31
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_571] 0 - 0.30
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_19] 1 True 10.02
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6587s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18736873 bytes MEM: Free's : 26 free's of 18736873 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_785] 0 - 0.31
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_164] 1 True 8.93
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.219s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2555s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2561s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18829021 bytes MEM: Free's : 26 free's of 18829021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_493] 1 True 10.91
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5901s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5914s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38845925 bytes MEM: Free's : 26 free's of 38845925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_696] 0 - 0.33
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_152] 1 True 11.67
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2496s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18829013 bytes MEM: Free's : 26 free's of 18829013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_94] 1 True 11.15
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.53s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.54s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18748305 bytes MEM: Free's : 26 free's of 18748305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_297] 1 True 14.05
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6722s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6737s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27254677 bytes MEM: Free's : 26 free's of 27254677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_849] 0 - 0.22
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_53] 1 True 16.51
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5160s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5171s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730529 bytes MEM: Free's : 26 free's of 18730529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_106] 1 True 13.80
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.380s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5893s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5908s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18734749 bytes MEM: Free's : 26 free's of 18734749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_403] 1 True 11.32
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7556s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 77005073 bytes MEM: Free's : 26 free's of 77005073 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_782] 0 - 0.27
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_514] 1 True 14.07
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.220s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2152s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2158s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 80924377 bytes MEM: Free's : 26 free's of 80924377 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_854] 0 - 0.27
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_75] 1 True 13.42
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6037s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6048s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729485 bytes MEM: Free's : 26 free's of 18729485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_124] 1 True 10.78
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.415s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7146s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18768593 bytes MEM: Free's : 26 free's of 18768593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_644] 0 - 0.32
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_479] 1 True 15.94
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.215s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2013s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2022s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47261881 bytes MEM: Free's : 26 free's of 47261881 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_256] 1 True 11.78
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.384s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5905s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21053401 bytes MEM: Free's : 26 free's of 21053401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_1] 1 True 10.81
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.233s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2068s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2076s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18732657 bytes MEM: Free's : 26 free's of 18732657 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_203] 1 True 11.08
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4926s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19967725 bytes MEM: Free's : 26 free's of 19967725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_459] 1 True 14.72
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46735401 bytes MEM: Free's : 26 free's of 46735401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_151] 1 True 10.13
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4523s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18812625 bytes MEM: Free's : 26 free's of 18812625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_39] 1 True 12.46
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.428s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6286s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731153 bytes MEM: Free's : 26 free's of 18731153 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_768] 0 - 0.26
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_54] 1 True 13.53
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.231s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2224s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730529 bytes MEM: Free's : 26 free's of 18730529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_598] 0 - 0.32
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_837] 0 - 0.33
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_60] 1 True 9.85
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.348s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5793s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730757 bytes MEM: Free's : 26 free's of 18730757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_632] 0 - 0.31
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_61] 1 True 11.53
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5666s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731069 bytes MEM: Free's : 26 free's of 18731069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_649] 0 - 0.27
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_441] 1 True 9.08
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3377s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47499285 bytes MEM: Free's : 26 free's of 47499285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_196] 1 True 9.26
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.257s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2758s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2767s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19836625 bytes MEM: Free's : 26 free's of 19836625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_8] 1 True 10.18
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5170s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18747293 bytes MEM: Free's : 26 free's of 18747293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_341] 1 True 10.02
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.217s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3739s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3744s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31113061 bytes MEM: Free's : 26 free's of 31113061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_156] 1 True 9.03
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18829013 bytes MEM: Free's : 26 free's of 18829013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_594] 0 - 0.26
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_472] 1 True 11.83
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.211s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2187s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2193s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44454661 bytes MEM: Free's : 26 free's of 44454661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_108] 1 True 9.94
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5499s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5509s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733677 bytes MEM: Free's : 26 free's of 18733677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_110] 1 True 12.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5926s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5940s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733677 bytes MEM: Free's : 26 free's of 18733677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_184] 1 True 12.19
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.405s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6549s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6562s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796437 bytes MEM: Free's : 26 free's of 18796437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_852] 0 - 0.25
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_376] 1 True 8.61
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.378s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6127s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6142s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58310361 bytes MEM: Free's : 26 free's of 58310361 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_65] 1 True 11.57
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.364s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5947s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5956s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731069 bytes MEM: Free's : 26 free's of 18731069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_305] 1 True 11.91
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7918s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7935s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27242341 bytes MEM: Free's : 26 free's of 27242341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_532] 1 True 10.28
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.387s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6559s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6572s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73243301 bytes MEM: Free's : 26 free's of 73243301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_56] 1 True 8.51
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4291s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4296s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730757 bytes MEM: Free's : 26 free's of 18730757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_817] 0 - 0.29
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_879] 0 - 0.19
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_525] 1 True 9.16
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6219s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 77429981 bytes MEM: Free's : 26 free's of 77429981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_247] 1 True 9.61
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6430s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6441s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21256925 bytes MEM: Free's : 26 free's of 21256925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_144] 1 True 10.10
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6957s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6969s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764641 bytes MEM: Free's : 26 free's of 18764641 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_135] 1 True 8.20
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5939s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5951s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18770685 bytes MEM: Free's : 26 free's of 18770685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_825] 0 - 0.25
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_821] 0 - 0.24
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_301] 1 True 14.73
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1016s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6237s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6249s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27242341 bytes MEM: Free's : 26 free's of 27242341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_625] 0 - 0.24
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_613] 0 - 0.25
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_897] 0 - 0.26
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_558] 0 - 0.28
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_456] 1 True 11.98
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5268s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46742513 bytes MEM: Free's : 26 free's of 46742513 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_127] 1 True 11.10
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5914s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5922s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18768593 bytes MEM: Free's : 26 free's of 18768593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_132] 1 True 11.55
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4286s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4292s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18766557 bytes MEM: Free's : 26 free's of 18766557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_491] 1 True 9.56
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.434s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6292s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38843137 bytes MEM: Free's : 26 free's of 38843137 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_847] 0 - 0.26
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_798] 0 - 0.25
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_447] 1 True 10.30
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5507s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5520s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 48266725 bytes MEM: Free's : 26 free's of 48266725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_467] 1 True 10.89
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4675s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46731997 bytes MEM: Free's : 26 free's of 46731997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_518] 1 True 12.10
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.214s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2626s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2632s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96300177 bytes MEM: Free's : 26 free's of 96300177 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_312] 1 True 9.40
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4538s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4547s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 43400917 bytes MEM: Free's : 26 free's of 43400917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_149] 1 True 8.86
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5203s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764641 bytes MEM: Free's : 26 free's of 18764641 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_666] 0 - 0.26
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_647] 0 - 0.28
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_239] 1 True 7.73
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.177s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3136s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3143s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21461713 bytes MEM: Free's : 26 free's of 21461713 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_102] 1 True 15.42
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4541s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4548s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733677 bytes MEM: Free's : 26 free's of 18733677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_148] 1 True 9.45
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764929 bytes MEM: Free's : 26 free's of 18764929 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_603] 0 - 0.30
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_665] 0 - 0.28
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_893] 0 - 0.26
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_861] 0 - 0.29
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_869] 0 - 0.24
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_650] 0 - 0.21
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_87] 1 True 11.53
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5107s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5117s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729449 bytes MEM: Free's : 26 free's of 18729449 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_894] 0 - 0.21
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_510] 1 True 9.39
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.369s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38840749 bytes MEM: Free's : 26 free's of 38840749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_140] 1 True 9.72
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18765525 bytes MEM: Free's : 26 free's of 18765525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_481] 1 True 8.38
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.230s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2026s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39308269 bytes MEM: Free's : 26 free's of 39308269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_808] 0 - 0.19
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_517] 1 True 9.48
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6228s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6238s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96300177 bytes MEM: Free's : 26 free's of 96300177 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_63] 1 True 9.46
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.348s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5179s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5187s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18735901 bytes MEM: Free's : 26 free's of 18735901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_185] 1 True 12.52
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.238s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3129s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3137s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796389 bytes MEM: Free's : 26 free's of 18796389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_261] 1 True 8.68
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4781s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4791s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21052261 bytes MEM: Free's : 26 free's of 21052261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_353] 1 True 12.80
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.208s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2552s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74034897 bytes MEM: Free's : 26 free's of 74034897 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_89] 1 True 8.74
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.255s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729449 bytes MEM: Free's : 26 free's of 18729449 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_790] 0 - 0.25
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_655] 0 - 0.30
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_211] 1 True 10.88
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.215s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5238s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5244s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19706585 bytes MEM: Free's : 26 free's of 19706585 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_352] 1 True 12.89
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4874s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4879s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74034897 bytes MEM: Free's : 26 free's of 74034897 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_561] 0 - 0.27
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_432] 1 True 10.41
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.245s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70904305 bytes MEM: Free's : 26 free's of 70904305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_617] 0 - 0.28
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_290] 1 True 10.98
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.238s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2570s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27504341 bytes MEM: Free's : 26 free's of 27504341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_227] 1 True 9.51
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4413s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19705701 bytes MEM: Free's : 26 free's of 19705701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_349] 1 True 10.60
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5786s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5799s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31113061 bytes MEM: Free's : 26 free's of 31113061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_519] 1 True 8.96
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.188s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1915s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1920s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 80924377 bytes MEM: Free's : 26 free's of 80924377 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_425] 1 True 10.82
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.184s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1717s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76209881 bytes MEM: Free's : 26 free's of 76209881 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_794] 0 - 0.22
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_114] 1 True 8.44
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5231s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733181 bytes MEM: Free's : 26 free's of 18733181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_48] 1 True 8.52
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.234s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3281s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730565 bytes MEM: Free's : 26 free's of 18730565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_866] 0 - 0.24
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_629] 0 - 0.23
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_507] 1 True 8.91
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.215s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2427s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2434s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38840501 bytes MEM: Free's : 26 free's of 38840501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_880] 0 - 0.22
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_699] 0 - 0.22
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_424] 1 True 10.29
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3650s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76209457 bytes MEM: Free's : 26 free's of 76209457 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_380] 1 True 11.42
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.396s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5933s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5944s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58331029 bytes MEM: Free's : 26 free's of 58331029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_43] 1 True 9.36
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6118s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6129s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730565 bytes MEM: Free's : 26 free's of 18730565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_818] 0 - 0.20
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_589] 0 - 0.21
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_179] 1 True 12.71
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3941s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796761 bytes MEM: Free's : 26 free's of 18796761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_870] 0 - 0.23
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_328] 1 True 9.16
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5623s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5633s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31522517 bytes MEM: Free's : 26 free's of 31522517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_177] 1 True 12.19
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796761 bytes MEM: Free's : 26 free's of 18796761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_872] 0 - 0.24
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_269] 1 True 9.51
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5097s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21052261 bytes MEM: Free's : 26 free's of 21052261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_435] 1 True 10.14
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.189s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2396s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70904305 bytes MEM: Free's : 26 free's of 70904305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_420] 1 True 10.23
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5943s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5953s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76212869 bytes MEM: Free's : 26 free's of 76212869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_562] 0 - 0.20
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_321] 1 True 9.55
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4478s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4484s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31522517 bytes MEM: Free's : 26 free's of 31522517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_306] 1 True 9.06
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.207s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2198s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2203s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27242341 bytes MEM: Free's : 26 free's of 27242341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_661] 0 - 0.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_419] 1 True 8.86
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4200s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4205s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76212869 bytes MEM: Free's : 26 free's of 76212869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_160] 1 True 10.73
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.245s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3917s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3923s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18812625 bytes MEM: Free's : 26 free's of 18812625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_910] 0 - 0.24
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_670] 0 - 0.29
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_545] 1 True 9.15
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.260s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4163s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73236653 bytes MEM: Free's : 26 free's of 73236653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_602] 0 - 0.28
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_31] 1 True 9.45
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.257s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4490s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4497s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731153 bytes MEM: Free's : 26 free's of 18731153 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_592] 0 - 0.28
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_671] 0 - 0.30
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_580] 0 - 0.35
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_526] 1 True 9.17
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.245s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3453s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 75333293 bytes MEM: Free's : 26 free's of 75333293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_779] 0 - 0.19
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_365] 1 True 9.06
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.232s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2627s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 61452005 bytes MEM: Free's : 26 free's of 61452005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_168] 1 True 8.32
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18829021 bytes MEM: Free's : 26 free's of 18829021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_641] 0 - 0.21
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_819] 0 - 0.14
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_868] 0 - 0.20
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_363] 1 True 8.69
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3086s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3097s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 61452005 bytes MEM: Free's : 26 free's of 61452005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_780] 0 - 0.16
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_882] 0 - 0.15
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_310] 1 True 9.42
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5282s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5289s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27242589 bytes MEM: Free's : 26 free's of 27242589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_588] 0 - 0.16
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_45] 1 True 7.99
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4804s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731525 bytes MEM: Free's : 26 free's of 18731525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_253] 1 True 9.53
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6695s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6703s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21057277 bytes MEM: Free's : 26 free's of 21057277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_691] 0 - 0.20
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_462] 1 True 9.03
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6602s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6619s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46732069 bytes MEM: Free's : 26 free's of 46732069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_42] 1 True 12.05
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5799s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5812s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730621 bytes MEM: Free's : 26 free's of 18730621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_752] 0 - 0.18
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_824] 0 - 0.20
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_905] 0 - 0.19
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_378] 1 True 11.32
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.231s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3230s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3238s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58318577 bytes MEM: Free's : 26 free's of 58318577 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_555] 0 - 0.21
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_522] 1 True 13.10
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5312s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73935501 bytes MEM: Free's : 26 free's of 73935501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_84] 1 True 10.32
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.245s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3718s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3725s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729449 bytes MEM: Free's : 26 free's of 18729449 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_111] 1 True 11.07
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.199s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2955s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2961s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733389 bytes MEM: Free's : 26 free's of 18733389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_574] 0 - 0.22
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_270] 1 True 9.25
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.376s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5699s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5709s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21052261 bytes MEM: Free's : 26 free's of 21052261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_407] 1 True 12.89
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4933s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4941s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 78596401 bytes MEM: Free's : 26 free's of 78596401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_47] 1 True 10.11
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5264s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730565 bytes MEM: Free's : 26 free's of 18730565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_150] 1 True 8.44
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6045s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764661 bytes MEM: Free's : 26 free's of 18764661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_648] 0 - 0.26
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_651] 0 - 0.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_393] 1 True 10.57
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.250s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4070s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 86552941 bytes MEM: Free's : 26 free's of 86552941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_477] 1 True 9.87
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.268s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3717s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3724s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44454661 bytes MEM: Free's : 26 free's of 44454661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_222] 1 True 10.78
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.203s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2213s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19705949 bytes MEM: Free's : 26 free's of 19705949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_751] 0 - 0.24
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_289] 1 True 9.40
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.194s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1917s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1924s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27504341 bytes MEM: Free's : 26 free's of 27504341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_426] 1 True 9.60
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.209s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1891s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1895s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76209433 bytes MEM: Free's : 26 free's of 76209433 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_178] 1 True 10.48
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.228s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2793s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2800s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18797809 bytes MEM: Free's : 26 free's of 18797809 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_267] 1 True 8.97
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.219s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2122s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2130s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21052309 bytes MEM: Free's : 26 free's of 21052309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_859] 0 - 0.21
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_5] 1 True 8.81
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.188s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2651s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731317 bytes MEM: Free's : 26 free's of 18731317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_189] 1 True 9.88
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4698s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4705s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796437 bytes MEM: Free's : 26 free's of 18796437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_777] 0 - 0.20
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_288] 1 True 10.88
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4910s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4917s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28815101 bytes MEM: Free's : 26 free's of 28815101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_463] 1 True 12.63
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.367s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46731997 bytes MEM: Free's : 26 free's of 46731997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_26] 1 True 11.91
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729997 bytes MEM: Free's : 26 free's of 18729997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_408] 1 True 9.28
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.365s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6638s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6656s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 77005073 bytes MEM: Free's : 26 free's of 77005073 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_630] 0 - 0.28
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_499] 1 True 11.02
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.204s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2721s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38843137 bytes MEM: Free's : 26 free's of 38843137 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_287] 1 True 10.58
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.344s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5507s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5516s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27766493 bytes MEM: Free's : 26 free's of 27766493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_232] 1 True 10.76
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4425s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22280921 bytes MEM: Free's : 26 free's of 22280921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_299] 1 True 9.77
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4575s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4586s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27246309 bytes MEM: Free's : 26 free's of 27246309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_675] 0 - 0.35
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_553] 0 - 0.18
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_27] 1 True 13.59
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.354s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6003s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729997 bytes MEM: Free's : 26 free's of 18729997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_554] 0 - 0.21
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_834] 0 - 0.22
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_238] 1 True 10.51
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.235s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4003s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4007s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24124133 bytes MEM: Free's : 26 free's of 24124133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_303] 1 True 7.54
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4495s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4501s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27242341 bytes MEM: Free's : 26 free's of 27242341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_192] 1 True 9.79
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4802s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4808s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19967701 bytes MEM: Free's : 26 free's of 19967701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_528] 1 True 12.06
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4506s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4512s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73935501 bytes MEM: Free's : 26 free's of 73935501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_304] 1 True 10.76
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4581s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4585s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27242389 bytes MEM: Free's : 26 free's of 27242389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_136] 1 True 9.27
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4553s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18765525 bytes MEM: Free's : 26 free's of 18765525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_415] 1 True 8.72
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4187s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76212869 bytes MEM: Free's : 26 free's of 76212869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_3] 1 True 7.38
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.241s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3569s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3573s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731317 bytes MEM: Free's : 26 free's of 18731317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_524] 1 True 9.55
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4702s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4707s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 75333293 bytes MEM: Free's : 26 free's of 75333293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_896] 0 - 0.21
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_116] 1 True 8.60
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.192s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1740s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733161 bytes MEM: Free's : 26 free's of 18733161 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_143] 1 True 8.58
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.183s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2798s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2803s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764681 bytes MEM: Free's : 26 free's of 18764681 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_860] 0 - 0.16
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_216] 1 True 8.52
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.184s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2952s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19707621 bytes MEM: Free's : 26 free's of 19707621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_358] 1 True 10.44
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5326s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 97627861 bytes MEM: Free's : 26 free's of 97627861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_133] 1 True 10.06
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4811s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4818s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18765525 bytes MEM: Free's : 26 free's of 18765525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_787] 0 - 0.18
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_887] 0 - 0.23
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_909] 0 - 0.21
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_389] 1 True 9.62
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5614s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5621s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58306405 bytes MEM: Free's : 26 free's of 58306405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_796] 0 - 0.18
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_331] 1 True 9.15
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4067s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4074s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31115481 bytes MEM: Free's : 26 free's of 31115481 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_801] 0 - 0.18
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_863] 0 - 0.20
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_248] 1 True 10.24
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.219s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21359333 bytes MEM: Free's : 26 free's of 21359333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_688] 0 - 0.20
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_443] 1 True 11.21
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3258s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3261s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 48266725 bytes MEM: Free's : 26 free's of 48266725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_773] 0 - 0.17
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_830] 0 - 0.16
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_600] 0 - 0.18
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_505] 1 True 10.49
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4223s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38840501 bytes MEM: Free's : 26 free's of 38840501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_396] 1 True 11.43
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4019s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4024s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96896601 bytes MEM: Free's : 26 free's of 96896601 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_322] 1 True 9.50
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.197s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2736s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2742s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33570557 bytes MEM: Free's : 26 free's of 33570557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_208] 1 True 10.66
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4818s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4826s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19967725 bytes MEM: Free's : 26 free's of 19967725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_125] 1 True 10.14
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.196s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2662s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18768593 bytes MEM: Free's : 26 free's of 18768593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_795] 0 - 0.16
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_230] 1 True 9.24
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.218s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1882s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1889s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19705701 bytes MEM: Free's : 26 free's of 19705701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_476] 1 True 10.29
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.230s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3570s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41647569 bytes MEM: Free's : 26 free's of 41647569 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_765] 0 - 0.18
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_320] 1 True 10.22
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.186s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1660s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1665s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36028113 bytes MEM: Free's : 26 free's of 36028113 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_193] 1 True 10.37
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.227s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3570s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3574s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19836625 bytes MEM: Free's : 26 free's of 19836625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_174] 1 True 8.99
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.172s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2893s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2896s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18797285 bytes MEM: Free's : 26 free's of 18797285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_356] 1 True 9.14
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1229s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74034897 bytes MEM: Free's : 26 free's of 74034897 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_487] 1 True 8.31
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1371s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40243981 bytes MEM: Free's : 26 free's of 40243981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_471] 1 True 7.53
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1494s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44454661 bytes MEM: Free's : 26 free's of 44454661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_874] 0 - 0.19
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_281] 1 True 6.54
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1355s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27504341 bytes MEM: Free's : 26 free's of 27504341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_323] 1 True 5.52
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1330s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33570557 bytes MEM: Free's : 26 free's of 33570557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_575] 0 - 0.10
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_327] 1 True 6.60
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7611s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7619s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34799509 bytes MEM: Free's : 26 free's of 34799509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_886] 0 - 0.09
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_552] 0 - 0.09
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_175] 1 True 6.95
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.202s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2272s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2278s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796761 bytes MEM: Free's : 26 free's of 18796761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_282] 1 True 6.74
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5012s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5022s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29601685 bytes MEM: Free's : 26 free's of 29601685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_72] 1 True 6.27
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3918s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3923s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729485 bytes MEM: Free's : 26 free's of 18729485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_431] 1 True 7.62
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5670s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5681s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53638353 bytes MEM: Free's : 26 free's of 53638353 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_591] 0 - 0.09
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_10] 1 True 7.93
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4881s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4888s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18734821 bytes MEM: Free's : 26 free's of 18734821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_104] 1 True 8.70
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.383s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18735285 bytes MEM: Free's : 26 free's of 18735285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_891] 0 - 0.16
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_565] 0 - 0.18
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_180] 1 True 8.05
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.374s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5716s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5732s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18801081 bytes MEM: Free's : 26 free's of 18801081 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_606] 0 - 0.20
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_22] 1 True 8.35
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4966s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730225 bytes MEM: Free's : 26 free's of 18730225 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_307] 1 True 13.16
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27242365 bytes MEM: Free's : 26 free's of 27242365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_202] 1 True 9.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.196s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1758s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1761s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19771093 bytes MEM: Free's : 26 free's of 19771093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_445] 1 True 8.03
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.230s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2143s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2150s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47499285 bytes MEM: Free's : 26 free's of 47499285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_474] 1 True 8.99
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.150s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1598s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44454661 bytes MEM: Free's : 26 free's of 44454661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_329] 1 True 9.00
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.200s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2958s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2965s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31522517 bytes MEM: Free's : 26 free's of 31522517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_564] 0 - 0.22
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_103] 1 True 12.40
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.204s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2672s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2679s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18734749 bytes MEM: Free's : 26 free's of 18734749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_457] 1 True 10.12
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.203s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1853s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1858s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46763721 bytes MEM: Free's : 26 free's of 46763721 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_113] 1 True 10.07
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.268s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2165s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733201 bytes MEM: Free's : 26 free's of 18733201 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_903] 0 - 0.26
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_797] 0 - 0.22
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_99] 1 True 9.86
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4710s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4717s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18742573 bytes MEM: Free's : 26 free's of 18742573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_295] 1 True 9.71
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.174s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27248369 bytes MEM: Free's : 26 free's of 27248369 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_484] 1 True 9.32
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4651s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39308269 bytes MEM: Free's : 26 free's of 39308269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_430] 1 True 9.97
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4770s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4776s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76209457 bytes MEM: Free's : 26 free's of 76209457 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_318] 1 True 9.34
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.268s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4287s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4292s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50773721 bytes MEM: Free's : 26 free's of 50773721 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_422] 1 True 8.14
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4224s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4230s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76209481 bytes MEM: Free's : 26 free's of 76209481 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_30] 1 True 9.03
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.175s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6378s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729997 bytes MEM: Free's : 26 free's of 18729997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_542] 1 True 8.44
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.190s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1838s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73236629 bytes MEM: Free's : 26 free's of 73236629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_619] 0 - 0.20
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_509] 1 True 8.89
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.196s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1880s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1886s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38840549 bytes MEM: Free's : 26 free's of 38840549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_161] 1 True 8.26
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5657s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5668s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18812629 bytes MEM: Free's : 26 free's of 18812629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_2] 1 True 7.61
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4614s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4620s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18734821 bytes MEM: Free's : 26 free's of 18734821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_372] 1 True 10.14
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58318577 bytes MEM: Free's : 26 free's of 58318577 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_823] 0 - 0.14
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_51] 1 True 9.02
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6335s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730529 bytes MEM: Free's : 26 free's of 18730529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_569] 0 - 0.18
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_40] 1 True 8.73
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.182s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4016s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4027s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18735781 bytes MEM: Free's : 26 free's of 18735781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_620] 0 - 0.18
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_229] 1 True 8.71
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.377s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5597s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19705701 bytes MEM: Free's : 26 free's of 19705701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_271] 1 True 9.49
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.240s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2131s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2137s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29339345 bytes MEM: Free's : 26 free's of 29339345 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_535] 1 True 10.69
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4505s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73239953 bytes MEM: Free's : 26 free's of 73239953 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_25] 1 True 11.08
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.264s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3876s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3881s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730037 bytes MEM: Free's : 26 free's of 18730037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_18] 1 True 9.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4269s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4273s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18734833 bytes MEM: Free's : 26 free's of 18734833 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_531] 1 True 9.25
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2042s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2044s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73239953 bytes MEM: Free's : 26 free's of 73239953 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_375] 1 True 8.95
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.199s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2394s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2399s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58314469 bytes MEM: Free's : 26 free's of 58314469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_212] 1 True 9.35
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4534s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4539s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19708657 bytes MEM: Free's : 26 free's of 19708657 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_771] 0 - 0.21
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_689] 0 - 0.26
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_832] 0 - 0.22
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_599] 0 - 0.22
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_469] 1 True 8.76
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.211s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3162s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3166s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46732045 bytes MEM: Free's : 26 free's of 46732045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_511] 1 True 9.31
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.170s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96300177 bytes MEM: Free's : 26 free's of 96300177 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_635] 0 - 0.25
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_416] 1 True 10.20
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.174s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1713s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76216457 bytes MEM: Free's : 26 free's of 76216457 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_231] 1 True 8.95
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4998s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5005s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21871317 bytes MEM: Free's : 26 free's of 21871317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_559] 0 - 0.15
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_266] 1 True 8.15
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.205s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2839s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2843s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21052285 bytes MEM: Free's : 26 free's of 21052285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_478] 1 True 8.87
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4590s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41647569 bytes MEM: Free's : 26 free's of 41647569 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_579] 0 - 0.20
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_803] 0 - 0.18
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_568] 0 - 0.15
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_697] 0 - 0.14
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_67] 1 True 9.93
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4519s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730249 bytes MEM: Free's : 26 free's of 18730249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_845] 0 - 0.10
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_452] 1 True 8.85
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4900s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46735401 bytes MEM: Free's : 26 free's of 46735401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_4] 1 True 8.67
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.215s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2532s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2538s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18734821 bytes MEM: Free's : 26 free's of 18734821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_911] 0 - 0.17
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_373] 1 True 8.97
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2630s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58310361 bytes MEM: Free's : 26 free's of 58310361 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_783] 0 - 0.16
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_811] 0 - 0.15
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_348] 1 True 8.27
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4104s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4110s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31113061 bytes MEM: Free's : 26 free's of 31113061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_595] 0 - 0.19
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_885] 0 - 0.17
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_853] 0 - 0.22
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_264] 1 True 10.99
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4135s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4140s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21052285 bytes MEM: Free's : 26 free's of 21052285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_23] 1 True 10.86
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.221s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3624s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3629s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730225 bytes MEM: Free's : 26 free's of 18730225 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_254] 1 True 10.48
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1827s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1830s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21053401 bytes MEM: Free's : 26 free's of 21053401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_660] 0 - 0.40
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_308] 1 True 9.23
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4830s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4838s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27242589 bytes MEM: Free's : 26 free's of 27242589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_590] 0 - 0.20
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_233] 1 True 8.48
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.182s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1876s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1882s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21461713 bytes MEM: Free's : 26 free's of 21461713 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_672] 0 - 0.23
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_497] 1 True 9.99
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5605s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38843137 bytes MEM: Free's : 26 free's of 38843137 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_685] 0 - 0.23
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_667] 0 - 0.18
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_29] 1 True 9.55
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.208s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3929s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729997 bytes MEM: Free's : 26 free's of 18729997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_131] 1 True 7.67
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.188s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1658s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1663s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18765525 bytes MEM: Free's : 26 free's of 18765525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_875] 0 - 0.21
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_816] 0 - 0.29
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_260] 1 True 9.57
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3628s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3631s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21053401 bytes MEM: Free's : 26 free's of 21053401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_826] 0 - 0.16
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_147] 1 True 8.05
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4631s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4639s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764681 bytes MEM: Free's : 26 free's of 18764681 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_640] 0 - 0.17
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_906] 0 - 0.15
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_146] 1 True 8.37
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.222s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3397s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3400s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764641 bytes MEM: Free's : 26 free's of 18764641 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_758] 0 - 0.09
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_199] 1 True 9.67
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.171s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1535s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19836625 bytes MEM: Free's : 26 free's of 19836625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_401] 1 True 9.06
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4834s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4843s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 77005073 bytes MEM: Free's : 26 free's of 77005073 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_865] 0 - 0.18
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_315] 1 True 9.83
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4649s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 43400917 bytes MEM: Free's : 26 free's of 43400917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_417] 1 True 13.20
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.205s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1772s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76212869 bytes MEM: Free's : 26 free's of 76212869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_276] 1 True 8.88
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.333s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5022s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5029s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29339345 bytes MEM: Free's : 26 free's of 29339345 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_770] 0 - 0.16
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_38] 1 True 12.78
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4394s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4400s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731153 bytes MEM: Free's : 26 free's of 18731153 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_503] 1 True 12.41
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38840549 bytes MEM: Free's : 26 free's of 38840549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_278] 1 True 12.17
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5325s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29339345 bytes MEM: Free's : 26 free's of 29339345 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_587] 0 - 0.20
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_339] 1 True 12.21
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.202s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31118053 bytes MEM: Free's : 26 free's of 31118053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_334] 1 True 11.62
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.158s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1959s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1963s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31115481 bytes MEM: Free's : 26 free's of 31115481 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_129] 1 True 10.90
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.184s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1969s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1974s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18768593 bytes MEM: Free's : 26 free's of 18768593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_7] 1 True 10.88
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.249s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4188s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4193s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18732657 bytes MEM: Free's : 26 free's of 18732657 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_91] 1 True 11.24
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.261s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3849s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3853s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18754037 bytes MEM: Free's : 26 free's of 18754037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_489] 1 True 11.41
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39308269 bytes MEM: Free's : 26 free's of 39308269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_764] 0 - 0.22
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_319] 1 True 10.90
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.165s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 43400917 bytes MEM: Free's : 26 free's of 43400917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_213] 1 True 9.78
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.158s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2494s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19711893 bytes MEM: Free's : 26 free's of 19711893 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_194] 1 True 9.36
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.138s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2312s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19967701 bytes MEM: Free's : 26 free's of 19967701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_762] 0 - 0.18
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_684] 0 - 0.14
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_643] 0 - 0.15
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_130] 1 True 7.87
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1904s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18768593 bytes MEM: Free's : 26 free's of 18768593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_835] 0 - 0.15
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_529] 1 True 7.76
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1539s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 75333293 bytes MEM: Free's : 26 free's of 75333293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_300] 1 True 6.14
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.209s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3246s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3253s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27244249 bytes MEM: Free's : 26 free's of 27244249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_117] 1 True 5.63
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.245s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4661s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4668s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733389 bytes MEM: Free's : 26 free's of 18733389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_534] 1 True 6.08
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.203s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2312s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73246649 bytes MEM: Free's : 26 free's of 73246649 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_883] 0 - 0.09
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_32] 1 True 6.37
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4579s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4586s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731925 bytes MEM: Free's : 26 free's of 18731925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_332] 1 True 17.20
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4738s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31115481 bytes MEM: Free's : 26 free's of 31115481 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_439] 1 True 19.81
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5174s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5181s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53638353 bytes MEM: Free's : 26 free's of 53638353 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_605] 0 - 0.13
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_902] 0 - 0.12
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_50] 1 True 19.95
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5078s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5086s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730565 bytes MEM: Free's : 26 free's of 18730565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_914] 0 - 0.15
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_601] 0 - 0.18
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_844] 0 - 0.15
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_400] 1 True 19.31
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.209s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5068s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 86552941 bytes MEM: Free's : 26 free's of 86552941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_69] 1 True 17.40
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6062s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6067s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730249 bytes MEM: Free's : 26 free's of 18730249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_473] 1 True 18.09
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.168s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1522s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1527s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44454661 bytes MEM: Free's : 26 free's of 44454661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_812] 0 - 0.19
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_46] 1 True 16.48
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4057s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730805 bytes MEM: Free's : 26 free's of 18730805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_551] 0 - 0.20
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_397] 1 True 17.19
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1234s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 200332989 bytes MEM: Free's : 26 free's of 200332989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_784] 0 - 0.18
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_916] 0 - 0.21
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_494] 1 True 17.39
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5210s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5221s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38848713 bytes MEM: Free's : 26 free's of 38848713 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_141] 1 True 17.23
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.171s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1963s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1968s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764661 bytes MEM: Free's : 26 free's of 18764661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_85] 1 True 15.78
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.263s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3873s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3879s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729449 bytes MEM: Free's : 26 free's of 18729449 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_548] 1 True 15.44
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1323s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73236629 bytes MEM: Free's : 26 free's of 73236629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_236] 1 True 13.49
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.131s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2265s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2267s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21871317 bytes MEM: Free's : 26 free's of 21871317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_781] 0 - 0.25
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_789] 0 - 0.24
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_488] 1 True 14.27
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2099s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2101s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39308269 bytes MEM: Free's : 26 free's of 39308269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_379] 1 True 14.01
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2182s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58310361 bytes MEM: Free's : 26 free's of 58310361 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_383] 1 True 4.51
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.169s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2282s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58306453 bytes MEM: Free's : 26 free's of 58306453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_361] 1 True 7.13
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.254s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3328s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 61452005 bytes MEM: Free's : 26 free's of 61452005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_237] 1 True 13.40
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4544s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22895325 bytes MEM: Free's : 26 free's of 22895325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_504] 1 True 6.95
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5703s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38840549 bytes MEM: Free's : 26 free's of 38840549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_277] 1 True 9.32
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.217s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2025s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2032s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34582233 bytes MEM: Free's : 26 free's of 34582233 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_186] 1 True 13.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4566s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4572s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796413 bytes MEM: Free's : 26 free's of 18796413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_429] 1 True 14.14
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.151s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1553s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1556s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76209433 bytes MEM: Free's : 26 free's of 76209433 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_241] 1 True 13.22
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5511s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5519s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21359333 bytes MEM: Free's : 26 free's of 21359333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_173] 1 True 12.83
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.250s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4011s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796761 bytes MEM: Free's : 26 free's of 18796761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_470] 1 True 13.67
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.211s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3120s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3124s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 46731997 bytes MEM: Free's : 26 free's of 46731997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_265] 1 True 12.25
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4866s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21052261 bytes MEM: Free's : 26 free's of 21052261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_838] 0 - 0.22
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_337] 1 True 12.00
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.236s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1935s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1939s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31123197 bytes MEM: Free's : 26 free's of 31123197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_607] 0 - 0.17
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_44] 1 True 12.62
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.261s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4119s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4123s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731101 bytes MEM: Free's : 26 free's of 18731101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_857] 0 - 0.18
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_890] 0 - 0.22
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_24] 1 True 12.37
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.160s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1852s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1857s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729997 bytes MEM: Free's : 26 free's of 18729997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_404] 1 True 13.49
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.147s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2538s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 78596401 bytes MEM: Free's : 26 free's of 78596401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_530] 1 True 12.26
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.197s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3136s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3141s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74634397 bytes MEM: Free's : 26 free's of 74634397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_895] 0 - 0.26
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_405] 1 True 7.81
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2232s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2235s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 77005073 bytes MEM: Free's : 26 free's of 77005073 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_262] 1 True 8.46
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2187s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2189s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21052261 bytes MEM: Free's : 26 free's of 21052261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_391] 1 True 7.13
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2162s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2164s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 153786561 bytes MEM: Free's : 26 free's of 153786561 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_243] 1 True 7.14
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5591s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5601s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21154517 bytes MEM: Free's : 26 free's of 21154517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_370] 1 True 8.80
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5293s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59354837 bytes MEM: Free's : 26 free's of 59354837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_336] 1 True 12.47
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.404s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5919s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5929s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31123197 bytes MEM: Free's : 26 free's of 31123197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_123] 1 True 11.73
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7109s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7123s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18768593 bytes MEM: Free's : 26 free's of 18768593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_570] 0 - 0.14
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_482] 1 True 12.26
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5249s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41647613 bytes MEM: Free's : 26 free's of 41647613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_690] 0 - 0.19
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_345] 1 True 13.82
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.198s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2381s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31113061 bytes MEM: Free's : 26 free's of 31113061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_73] 1 True 13.81
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.233s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3500s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3504s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729781 bytes MEM: Free's : 26 free's of 18729781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_820] 0 - 0.18
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_572] 0 - 0.20
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_68] 1 True 11.04
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5565s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5573s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730249 bytes MEM: Free's : 26 free's of 18730249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_360] 1 True 14.22
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.144s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1389s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74034897 bytes MEM: Free's : 26 free's of 74034897 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_850] 0 - 0.24
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_840] 0 - 0.23
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_224] 1 True 10.42
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4376s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4384s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19705725 bytes MEM: Free's : 26 free's of 19705725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_21] 1 True 13.22
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.177s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1704s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730017 bytes MEM: Free's : 26 free's of 18730017 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_412] 1 True 9.98
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.173s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2576s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2580s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76212869 bytes MEM: Free's : 26 free's of 76212869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_74] 1 True 8.80
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.209s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3328s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3333s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729485 bytes MEM: Free's : 26 free's of 18729485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_219] 1 True 8.02
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1407s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19708657 bytes MEM: Free's : 26 free's of 19708657 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_839] 0 - 0.14
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_616] 0 - 0.13
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_501] 1 True 7.46
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.134s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1469s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38840549 bytes MEM: Free's : 26 free's of 38840549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_170] 1 True 6.58
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1416s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1420s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18878189 bytes MEM: Free's : 26 free's of 18878189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_371] 1 True 7.01
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.247s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3580s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3585s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58310361 bytes MEM: Free's : 26 free's of 58310361 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_614] 0 - 0.09
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_86] 1 True 7.82
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1303s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729677 bytes MEM: Free's : 26 free's of 18729677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_480] 1 True 8.98
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.231s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3482s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3485s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 47261881 bytes MEM: Free's : 26 free's of 47261881 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_107] 1 True 8.30
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.155s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1880s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1884s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733677 bytes MEM: Free's : 26 free's of 18733677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_919] 0 - 0.11
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_912] 0 - 0.10
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_83] 1 True 8.62
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4429s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18729449 bytes MEM: Free's : 26 free's of 18729449 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_434] 1 True 8.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.150s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1517s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70904305 bytes MEM: Free's : 26 free's of 70904305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_805] 0 - 0.13
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_904] 0 - 0.11
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_340] 1 True 7.01
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.156s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1797s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1802s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31115481 bytes MEM: Free's : 26 free's of 31115481 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_16] 1 True 7.84
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.204s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3264s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3268s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731321 bytes MEM: Free's : 26 free's of 18731321 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_520] 1 True 8.19
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.243s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3224s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3228s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96300177 bytes MEM: Free's : 26 free's of 96300177 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_326] 1 True 6.94
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1303s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1306s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31932125 bytes MEM: Free's : 26 free's of 31932125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_695] 0 - 0.10
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_195] 1 True 6.93
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.132s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1503s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19967701 bytes MEM: Free's : 26 free's of 19967701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_58] 1 True 6.22
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1531s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1533s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730529 bytes MEM: Free's : 26 free's of 18730529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_560] 0 - 0.11
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_171] 1 True 4.68
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1534s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1536s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18796761 bytes MEM: Free's : 26 free's of 18796761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_633] 0 - 0.06
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_385] 1 True 6.28
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1340s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58306429 bytes MEM: Free's : 26 free's of 58306429 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_34] 1 True 4.99
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731153 bytes MEM: Free's : 26 free's of 18731153 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_122] 1 True 2.02
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.148s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2897s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793189 bytes MEM: Free's : 26 free's of 18793189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_284] 1 True 1.88
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1418s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1420s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28028645 bytes MEM: Free's : 26 free's of 28028645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_198] 1 True 1.87
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2212s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2214s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19967701 bytes MEM: Free's : 26 free's of 19967701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_615] 0 - 0.08
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_206] 1 True 1.82
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.172s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3722s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3726s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19836637 bytes MEM: Free's : 26 free's of 19836637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_369] 1 True 1.97
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1739s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1741s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 61452005 bytes MEM: Free's : 26 free's of 61452005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_350] 1 True 1.99
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1684s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31113061 bytes MEM: Free's : 26 free's of 31113061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_258] 1 True 2.02
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1642s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1644s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21053401 bytes MEM: Free's : 26 free's of 21053401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_678] 0 - 0.09
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_898] 0 - 0.08
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_656] 0 - 0.08
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_197] 1 True 1.97
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.145s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2554s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19836625 bytes MEM: Free's : 26 free's of 19836625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_11] 1 True 1.78
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.128s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2869s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731321 bytes MEM: Free's : 26 free's of 18731321 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_394] 1 True 2.13
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2065s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2068s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96896601 bytes MEM: Free's : 26 free's of 96896601 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_272] 1 True 1.86
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1175s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1176s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29339345 bytes MEM: Free's : 26 free's of 29339345 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_618] 0 - 0.08
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_165] 1 True 1.91
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.162s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3272s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18927357 bytes MEM: Free's : 26 free's of 18927357 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_225] 1 True 1.84
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1132s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19705725 bytes MEM: Free's : 26 free's of 19705725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_28] 1 True 1.79
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730017 bytes MEM: Free's : 26 free's of 18730017 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_475] 1 True 1.96
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.136s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2078s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2080s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41647569 bytes MEM: Free's : 26 free's of 41647569 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_637] 0 - 0.07
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_913] 0 - 0.05
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_621] 0 - 0.07
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_120] 1 True 1.87
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.255s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1489s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733161 bytes MEM: Free's : 26 free's of 18733161 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_683] 0 - 0.09
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_495] 1 True 1.85
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.131s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2473s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2475s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38848713 bytes MEM: Free's : 26 free's of 38848713 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_628] 0 - 0.08
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_763] 0 - 0.08
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_286] 1 True 1.89
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.157s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3164s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27504341 bytes MEM: Free's : 26 free's of 27504341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_377] 1 True 1.85
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.169s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3511s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3515s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58318577 bytes MEM: Free's : 26 free's of 58318577 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_384] 1 True 2.02
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.139s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2679s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2683s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58306405 bytes MEM: Free's : 26 free's of 58306405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_809] 0 - 0.06
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 6 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_759] 0 - 0.07
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_652] 0 - 0.07
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------ | ScatterND | output | Maximum number of input dimension supported is 4, found 5 input dimensions | ------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_541] 1 True 1.99
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.136s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2740s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2743s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 73236677 bytes MEM: Free's : 26 free's of 73236677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_374] 1 True 1.90
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2068s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2071s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58314469 bytes MEM: Free's : 26 free's of 58314469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_343] 1 True 1.77
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1485s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31113061 bytes MEM: Free's : 26 free's of 31113061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_163] 1 True 1.88
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 2 | | TIDL_ScatterElementsLayer | 1 | 1 | ------------------------------------------------------------------------------------ Total nodes in subgraph: 9 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1471s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18829021 bytes MEM: Free's : 26 free's of 18829021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!